Output ringing is the voltage oscillation at an output terminal of an integrated circuit device caused by the parasitic inductance in the integrated circuit package and wiring. The faster the output switching speed, the greater the voltage oscillation swing at the output terminal.
Standard CMOS TTL (complementary metal oxide semiconductor transistor transistor logic) circuits have been plagued with output ringing as the switching rise and fall times of its output buffer reaches for instance around 10 ns (nano seconds). The ringing on the output terminal of the standard CMOS TTL circuit can raise the output logic low level about the required TTL specification, and thus cause the circuit to fail to measure up to its required access time.
CMOS output driver circuits used in many integrated circuit (IC) devices have a n-channel pull-down transistor and use sophisticated timing delay schemes in combination with the pull-down transistor in an attempt to reduce the output ringing to an acceptable level. However, at super high switching speeds, for instance around under 10 ns access times, timing delays are vulnerable to integration circuit process variations. Additionally, circuits incorporating such schemes are difficult to design.